FPGA, ASIC and SoC describe different aspects of a chip. An FPGA provides programmable logic; an ASIC implements a specific hardware design; a system-on-chip integrates processing and peripherals. A SoC can contain fixed logic, programmable logic, or both. These are overlapping categories, not three mutually exclusive choices.
Choose an architecture for the workload
| Approach | Useful when | What to validate |
|---|---|---|
| FPGA | Custom interfaces, parallel processing or changeable hardware logic matter | Timing closure, resource use, memory bandwidth, bitstream security and power |
| Custom ASIC | A stable function and production volume justify custom silicon | Verification, physical design, test coverage, foundry costs and respin risk |
| Available MCU or application SoC | Existing processors and peripherals meet the requirements | Exact interfaces, software support, update paths and component availability |
| SoC FPGA | Software and programmable logic need close integration | Processor–fabric communication, boot chain and division of responsibilities |
AMD Zynq UltraScale+ MPSoC and Microchip PolarFire SoC illustrate the combined approach. A SoC does not necessarily run Linux or include a radio; check the exact device and external components.
An ASIC can optimize area, energy and throughput for a particular function, but there is no universal clock-speed multiplier over an FPGA. Compare the same algorithm, numeric precision, memory traffic and operating conditions. An FPGA may outperform CPU software for a parallel pipeline while still being a poor fit for a memory-bound workload.
Calculate cost instead of assuming a volume threshold
Non-recurring engineering (NRE) includes development, verification, tools and IP. A custom ASIC can additionally involve masks, foundry services, packaging and production-test development. FPGA work still requires verification, timing closure, board integration and production support.
For a simplified comparison, the break-even volume is:
V = (NRE_ASIC − NRE_FPGA) / (unit_FPGA − unit_ASIC)
This expression only applies when the FPGA unit cost is higher and both options meet the specification. Illustrative assumptions, not a supplier quote: an additional ASIC NRE of €900,000 and a unit-cost saving of €18 give a break-even of 50,000 units. Changing either assumption changes the result. Include yield, inventory, financing, qualification, schedule and support before making a procurement decision. There is no reliable universal €10,000–€150,000 FPGA price or 50,000-unit switching rule.
Updates and CRA obligations
Programmable fabric can support a hardware-logic update, provided the affected function is implemented there. Hard IP and external components remain fixed. ASIC and SoC products can also receive firmware, microcode or system-level mitigations where their architecture supports them. Some defects require a hardware revision; neither an automatic recall nor a guaranteed field fix follows from the chip category alone.
Under the CRA, assess the product in scope and its intended use. PSA Certified or other component evidence may help substantiate particular security properties; it does not transfer the supplier’s conformity to the complete product or establish a fixed percentage saving. The manufacturer remains responsible for integration, vulnerability handling and the applicable assessment. Article 14 reporting has applied since 11 September 2026; the main CRA requirements apply from 11 December 2027.
Production, migration and supply chain
FPGA devices can be production components, not only prototypes. For an FPGA-to-ASIC migration, review portable RTL separately from vendor IP, memories, clocking and interfaces. Plan equivalence checking, physical implementation and design-for-test; reusable RTL does not eliminate these tasks or guarantee a migration schedule.
For long-lived industrial, aerospace or defence products, check the exact part’s qualification, availability programme, tool access and update support. Vendor headquarters do not establish manufacturing origin, radiation qualification or export eligibility. Reprogrammability does not exempt a product from export controls: classify the hardware, software and technology, destination and end use.
Our engineering support
Inovasense can coordinate architecture trade-offs, FPGA development and hardware–software integration. Start with measurable requirements and supplier quotations, then validate a representative prototype before committing to custom silicon.
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Frequently asked questions
Are FPGA, ASIC and SoC mutually exclusive?
No. FPGA describes programmable logic, ASIC a specific hardware implementation, and SoC integration. A SoC can include an FPGA fabric as well as fixed processor and peripheral blocks.
At what volume does an ASIC become cheaper?
There is no universal threshold. Compare quoted NRE and unit costs for equivalent specifications, then account for yield, schedule, qualification, inventory and lifecycle support.
Can an ASIC security defect be fixed in the field?
Sometimes firmware, microcode or a system-level mitigation is sufficient. A defect in an unmodifiable hardware function may require a hardware change. The remedy depends on the defect and architecture.
Does a certified chip make the product CRA compliant?
No. Component certification supports only its assessed scope. The product manufacturer must establish conformity for the integrated product and maintain the applicable vulnerability-handling process.
Primary sources
Technical and regulatory references checked on 1 October 2026.