Field-Programmable Gate Array (FPGA)
An FPGA is a semiconductor device built from a matrix of configurable logic blocks (CLBs), programmable interconnects, and dedicated hardware blocks (DSP slices, block RAM, I/O transceivers) that can be reconfigured by the customer after manufacturing — hence the term “field-programmable”. Unlike a CPU or microcontroller that executes instructions sequentially, an FPGA implements digital logic in parallel, mapping algorithms directly to silicon. The global FPGA market reached $11.02 billion in 2026 and is forecast to grow at 12–14 % CAGR through 2030.
Key Facts
| Aspect | Detail |
|---|---|
| Architecture | Array of CLBs + LUTs (look-up tables) + flip-flops + DSP slices + block RAM |
| Programming language | VHDL or SystemVerilog (RTL); HLS supports C/C++ for some workloads |
| Configuration | Loaded from external flash at boot; reprogrammable in-field via JTAG or remote OTA |
| Typical clock speeds | 200–800 MHz (high-end devices reach 1 GHz with PLL-based regions) |
| Logic density (high-end) | Up to 9.4 million logic elements (Intel Agilex 9, 7nm); 1.9 M LUTs (AMD Versal Premium) |
| Power efficiency | 2–10× higher power than ASIC, but order-of-magnitude lower than CPU for parallel workloads |
| Time to working hardware | 3–6 months for mid-complexity design |
| NRE cost | €10K–€150K typical for complete RTL + PCB + verification |
How FPGAs Work
An FPGA’s fundamental building block is the Look-Up Table (LUT), a small piece of memory that implements any boolean function of N inputs (typically 4–6). Hundreds of thousands of LUTs are connected by a programmable routing fabric. Dedicated silicon blocks accelerate common operations: DSP slices for multiply-accumulate (essential for signal processing and AI), block RAM for on-chip data buffers, and high-speed serial transceivers (PCIe Gen4/5, 10G–112G Ethernet) for I/O.
When you “program” an FPGA, you describe the desired digital circuit in a Hardware Description Language (HDL) like VHDL or SystemVerilog. The vendor toolchain (AMD Vivado, Intel Quartus, Microchip Libero) synthesizes your HDL into a netlist, places it onto the physical fabric, routes the connections, and produces a bitstream that configures the chip at boot.
FPGA vs ASIC vs Microcontroller
| Criterion | FPGA | ASIC | Microcontroller (MCU) |
|---|---|---|---|
| Reconfigurability | Full — update in field | Fixed after fabrication | Firmware updates only |
| Time to market | 3–6 months | 12–24 months | Weeks to months |
| NRE cost | €10K–€150K | €500K–€10M+ | Minimal (eval boards) |
| Unit cost at 10K volume | €15–€200 | €2–€50 | €0.50–€15 |
| Parallelism | Native — thousands of ops/cycle | Native | Sequential (limited DMA) |
| Best for | Reconfigurable, low-medium volume, parallel | High-volume, fixed function | General-purpose embedded |
For decision frameworks, see our FPGA vs ASIC engineering guide.
Common Use Cases (2026)
FPGAs dominate applications where parallelism, low latency, or post-deployment updates matter:
- Defense and aerospace — Radar and sonar beamforming, missile guidance, electronic warfare. DO-254 certification is mandatory; radiation-tolerant families like Microchip RTG4 and AMD Versal AI Edge are used in space platforms.
- 5G and telecom infrastructure — Massive MIMO baseband, fronthaul (eCPRI), and packet processing in base stations. Deterministic latency is non-negotiable.
- Industrial automation — Real-time motor control, PLC accelerators, vision systems for machine inspection. EtherCAT, PROFINET, TSN protocols often implemented in FPGA fabric.
- High-frequency trading — Sub-microsecond market data parsing and order execution; FPGA is the only path to single-digit nanosecond latencies.
- Medical imaging — CT and MRI signal reconstruction, ultrasound beamforming with patient-safety-grade reliability.
- Edge AI acceleration — DPU (Deep Learning Processor Unit) overlays on AMD/Xilinx FPGAs for on-device neural network inference. See Edge AI.
- Video processing — 4K/8K real-time encoding, computer vision pipelines, broadcast equipment.
FPGA Vendors and Families (2026)
| Vendor | Flagship family | Process node | Max logic elements | Differentiator |
|---|---|---|---|---|
| AMD (Xilinx) | Versal AI Edge / Premium | 7nm | 1.9 M LUTs | Adaptive SoC + AI Engine tiles |
| Intel (Altera) | Agilex 9 | Intel 7 | 9.4 M LE | Highest density available |
| Lattice | Avant / Nexus | 16nm FD-SOI | 500K LUTs | Ultra-low power (15 mW idle) |
| Microchip | PolarFire / PolarFire SoC | 28nm | 481K LE | Radiation-tolerant; lowest static power |
| Efinix | Titanium Ti180 | 16nm | 180K LE | Hard RISC-V core; lowest cost per LUT |
| NanoXplore (EU) | NG-Large / NG-Ultra | 65nm | 540K LE | EU-sovereign space-grade FPGA |
For European hardware sovereignty projects, NanoXplore is significant — it’s the only EU-headquartered FPGA vendor with space-qualified silicon, aligned with the EU Chips Act.
When to Choose FPGA
Choose FPGA when one or more applies: your requirements may change (firmware-style updates for hardware), your production volume is below ~50,000 units, you need real-time deterministic signal processing, your design must be field-upgradable for evolving threats or protocols, or you need radiation tolerance and long product lifecycles (10–30 years). FPGA is typically the only option for sub-microsecond signal processing, custom interfaces, and reconfigurable defense systems.
Avoid FPGA when unit cost dominates (ASIC wins at >500K units), the workload fits a stock MCU + DSP library, or you lack hardware engineering capacity (FPGA development requires RTL design, timing closure, and high-speed PCB skills — not just “coding”).
Related Terms
- ASIC — Fixed-function alternative to FPGA for high-volume production
- SoC — System-on-Chip; SoC FPGAs integrate ARM/RISC-V cores with programmable logic
- RTL Design — The hardware description methodology used to program FPGAs
- VHDL — The primary HDL for European FPGA development
- DO-254 — Design assurance standard for FPGAs in airborne electronics
- Edge AI — FPGA-accelerated neural network inference at the device level
Inovasense FPGA Capabilities
Inovasense delivers end-to-end FPGA design services — from requirements analysis and architecture specification through RTL development (VHDL/SystemVerilog), constrained-random verification (UVM), timing closure, board design, and volume production. We work across AMD Versal, Intel Agilex, Lattice Avant, Microchip PolarFire, and NanoXplore for EU-sovereign defense applications. Our team has DO-254 project experience for airborne hardware and EU dual-use export compliance for FPGA-based systems shipped outside the EU.
Official References
- DO-254 / ED-80 — Design Assurance for Airborne Electronic Hardware — RTCA, the applicable FPGA design assurance standard for aviation
- EU Chips Act (Regulation 2023/1781) — €43B framework supporting EU semiconductor sovereignty including FPGA development
- IEEE 1076 (VHDL standard) — The IEEE-standardized HDL used for most European FPGA designs